This is an archive of the discontinued LLVM Phabricator instance.

craig.topper retitled this revision from [RISCV] Add assembler check to make temp register is different than dest register for vmsgeu.vx pseudo. to [RISCV] Have assembler check that the temp register is different than dest register for vmsgeu.vx pseudo..Apr 22 2021, 9:12 PM

LGTM.

HsiangKai accepted this revision.Apr 23 2021, 12:55 AM

This revision is now accepted and ready to land.Apr 23 2021, 12:55 AM

This revision was landed with ongoing or failed builds.Apr 23 2021, 9:40 AM

Closed by commit rGfae1d31c0917: [RISCV] Have assembler check that the temp register is different than dest… (authored by craig.topper). · Explain Why

This revision was automatically updated to reflect the committed changes.

craig.topper added a commit: rGfae1d31c0917: [RISCV] Have assembler check that the temp register is different than dest….

Revision Contents

Path

Size

llvm/

lib/

Target/

RISCV/

AsmParser/

RISCVAsmParser.cpp

11 lines

test/

MC/

RISCV/

rvv/

invalid.s

6 lines

Diff 340085

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

	Show First 20 Lines • Show All 2,455 Lines • ▼ Show 20 Lines

	std::unique_ptr<RISCVOperand> RISCVAsmParser::defaultMaskRegOp() const {			std::unique_ptr<RISCVOperand> RISCVAsmParser::defaultMaskRegOp() const {
	return RISCVOperand::createReg(RISCV::NoRegister, llvm::SMLoc(),			return RISCVOperand::createReg(RISCV::NoRegister, llvm::SMLoc(),
	llvm::SMLoc(), isRV64());			llvm::SMLoc(), isRV64());
	}			}

	bool RISCVAsmParser::validateInstruction(MCInst &Inst,			bool RISCVAsmParser::validateInstruction(MCInst &Inst,
	OperandVector &Operands) {			OperandVector &Operands) {
				if (Inst.getOpcode() == RISCV::PseudoVMSGEU_VX_M_T \|\|
				Inst.getOpcode() == RISCV::PseudoVMSGE_VX_M_T) {
				unsigned DestReg = Inst.getOperand(0).getReg();
				unsigned TempReg = Inst.getOperand(1).getReg();
				if (DestReg == TempReg) {
				SMLoc Loc = Operands.back()->getStartLoc();
				return Error(Loc, "The temporary vector register cannot be the same as "
				"the destination register.");
				}
				}

	const MCInstrDesc &MCID = MII.get(Inst.getOpcode());			const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
	unsigned Constraints =			unsigned Constraints =
	(MCID.TSFlags & RISCVII::ConstraintMask) >> RISCVII::ConstraintShift;			(MCID.TSFlags & RISCVII::ConstraintMask) >> RISCVII::ConstraintShift;
	if (Constraints == RISCVII::NoConstraint)			if (Constraints == RISCVII::NoConstraint)
	return false;			return false;

	unsigned DestReg = Inst.getOperand(0).getReg();			unsigned DestReg = Inst.getOperand(0).getReg();
	// Operands[1] will be the first operand, DestReg.			// Operands[1] will be the first operand, DestReg.
	▲ Show 20 Lines • Show All 211 Lines • Show Last 20 Lines

llvm/test/MC/RISCV/rvv/invalid.s

	Show First 20 Lines • Show All 660 Lines • ▼ Show 20 Lines
	vs8r.v v7, (a0)			vs8r.v v7, (a0)
	# CHECK-ERROR: invalid operand for instruction			# CHECK-ERROR: invalid operand for instruction

	vmsge.vx v2, v4, a0, v0.t, v0			vmsge.vx v2, v4, a0, v0.t, v0
	# CHECK-ERROR: invalid operand for instruction			# CHECK-ERROR: invalid operand for instruction

	vmsgeu.vx v2, v4, a0, v0.t, v0			vmsgeu.vx v2, v4, a0, v0.t, v0
	# CHECK-ERROR: invalid operand for instruction			# CHECK-ERROR: invalid operand for instruction

				vmsge.vx v2, v4, a0, v0.t, v2
				# CHECK-ERROR: The temporary vector register cannot be the same as the destination register.

				vmsgeu.vx v2, v4, a0, v0.t, v2
				# CHECK-ERROR: The temporary vector register cannot be the same as the destination register.

This is an archive of the discontinued LLVM Phabricator instance.

[RISCV] Have assembler check that the temp register is different than dest register for vmsgeu.vx pseudo.ClosedPublic

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Diff 340085

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

llvm/test/MC/RISCV/rvv/invalid.s

[RISCV] Have assembler check that the temp register is different than dest register for vmsgeu.vx pseudo.
ClosedPublic