Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -34,9 +34,18 @@ SDTCisInt<2>]>; def SDT_RISCVReadCycleWide : SDTypeProfile<2, 0, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; +def SDT_RISCVIntUnaryOpW : SDTypeProfile<1, 1, [ + SDTCisSameAs<0, 1>, SDTCisVT<0, i64> +]>; def SDT_RISCVIntBinOpW : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<0, i64> ]>; +def SDT_RISCVIntShiftOpW : SDTypeProfile<1, 2, [ + SDTCisSameAs<0, 1>, SDTCisVT<0, i64>, SDTCisVT<2, i64> +]>; +def SDT_RISCVIntShiftDOpW : SDTypeProfile<1, 3, [ + SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<0, i64>, SDTCisVT<3, i64> +]>; // Target-independent nodes, but with target-specific formats. def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart, @@ -62,9 +71,9 @@ def riscv_tail : SDNode<"RISCVISD::TAIL", SDT_RISCVCall, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; -def riscv_sllw : SDNode<"RISCVISD::SLLW", SDT_RISCVIntBinOpW>; -def riscv_sraw : SDNode<"RISCVISD::SRAW", SDT_RISCVIntBinOpW>; -def riscv_srlw : SDNode<"RISCVISD::SRLW", SDT_RISCVIntBinOpW>; +def riscv_sllw : SDNode<"RISCVISD::SLLW", SDT_RISCVIntShiftOpW>; +def riscv_sraw : SDNode<"RISCVISD::SRAW", SDT_RISCVIntShiftOpW>; +def riscv_srlw : SDNode<"RISCVISD::SRLW", SDT_RISCVIntShiftOpW>; def riscv_read_csr : SDNode<"RISCVISD::READ_CSR", SDT_RISCVReadCSR, [SDNPHasChain]>; def riscv_write_csr : SDNode<"RISCVISD::WRITE_CSR", SDT_RISCVWriteCSR, Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -17,18 +17,18 @@ // Operand and SDNode transformation definitions. //===----------------------------------------------------------------------===// -def riscv_clzw : SDNode<"RISCVISD::CLZW", SDTIntUnaryOp>; -def riscv_ctzw : SDNode<"RISCVISD::CTZW", SDTIntUnaryOp>; -def riscv_rolw : SDNode<"RISCVISD::ROLW", SDTIntShiftOp>; -def riscv_rorw : SDNode<"RISCVISD::RORW", SDTIntShiftOp>; -def riscv_fslw : SDNode<"RISCVISD::FSLW", SDTIntShiftDOp>; -def riscv_fsrw : SDNode<"RISCVISD::FSRW", SDTIntShiftDOp>; +def riscv_clzw : SDNode<"RISCVISD::CLZW", SDT_RISCVIntUnaryOpW>; +def riscv_ctzw : SDNode<"RISCVISD::CTZW", SDT_RISCVIntUnaryOpW>; +def riscv_rolw : SDNode<"RISCVISD::ROLW", SDT_RISCVIntShiftOpW>; +def riscv_rorw : SDNode<"RISCVISD::RORW", SDT_RISCVIntShiftOpW>; +def riscv_fslw : SDNode<"RISCVISD::FSLW", SDT_RISCVIntShiftDOpW>; +def riscv_fsrw : SDNode<"RISCVISD::FSRW", SDT_RISCVIntShiftDOpW>; def riscv_fsl : SDNode<"RISCVISD::FSL", SDTIntShiftDOp>; def riscv_fsr : SDNode<"RISCVISD::FSR", SDTIntShiftDOp>; def riscv_grevi : SDNode<"RISCVISD::GREVI", SDTIntBinOp>; -def riscv_greviw : SDNode<"RISCVISD::GREVIW", SDTIntBinOp>; +def riscv_greviw : SDNode<"RISCVISD::GREVIW", SDT_RISCVIntShiftOpW>; def riscv_gorci : SDNode<"RISCVISD::GORCI", SDTIntBinOp>; -def riscv_gorciw : SDNode<"RISCVISD::GORCIW", SDTIntBinOp>; +def riscv_gorciw : SDNode<"RISCVISD::GORCIW", SDT_RISCVIntShiftOpW>; def riscv_shfli : SDNode<"RISCVISD::SHFLI", SDTIntBinOp>; def UImmLog2XLenHalfAsmOperand : AsmOperandClass { @@ -850,37 +850,37 @@ } // Predicates = [HasStdExtZba, IsRV64] let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { -def : Pat<(i64 (riscv_rolw GPR:$rs1, GPR:$rs2)), +def : Pat<(riscv_rolw GPR:$rs1, GPR:$rs2), (ROLW GPR:$rs1, GPR:$rs2)>; -def : Pat<(i64 (riscv_rorw GPR:$rs1, GPR:$rs2)), +def : Pat<(riscv_rorw GPR:$rs1, GPR:$rs2), (RORW GPR:$rs1, GPR:$rs2)>; -def : Pat<(i64 (riscv_rorw GPR:$rs1, uimm5:$rs2)), +def : Pat<(riscv_rorw GPR:$rs1, uimm5:$rs2), (RORIW GPR:$rs1, uimm5:$rs2)>; -def : Pat<(i64 (riscv_rolw GPR:$rs1, uimm5:$rs2)), +def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2), (RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>; } // Predicates = [HasStdExtZbbOrZbp, IsRV64] let Predicates = [HasStdExtZbp, IsRV64] in { -def : Pat<(i64 (riscv_rorw (riscv_greviw GPR:$rs1, 24), (i64 16))), (GREVIW GPR:$rs1, 8)>; -def : Pat<(i64 (riscv_rolw (riscv_greviw GPR:$rs1, 24), (i64 16))), (GREVIW GPR:$rs1, 8)>; -def : Pat<(i64 (riscv_greviw GPR:$rs1, timm:$shamt)), (GREVIW GPR:$rs1, timm:$shamt)>; -def : Pat<(i64 (riscv_gorciw GPR:$rs1, timm:$shamt)), (GORCIW GPR:$rs1, timm:$shamt)>; +def : Pat<(riscv_rorw (riscv_greviw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>; +def : Pat<(riscv_rolw (riscv_greviw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>; +def : Pat<(riscv_greviw GPR:$rs1, timm:$shamt), (GREVIW GPR:$rs1, timm:$shamt)>; +def : Pat<(riscv_gorciw GPR:$rs1, timm:$shamt), (GORCIW GPR:$rs1, timm:$shamt)>; } // Predicates = [HasStdExtZbp, IsRV64] let Predicates = [HasStdExtZbt, IsRV64] in { -def : Pat<(i64 (riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2)), +def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2), (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>; -def : Pat<(i64 (riscv_fsrw GPR:$rs3, GPR:$rs1, GPR:$rs2)), +def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, GPR:$rs2), (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>; -def : Pat<(i64 (riscv_fsrw GPR:$rs3, GPR:$rs1, uimm5:$shamt)), +def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, uimm5:$shamt), (FSRIW GPR:$rs1, GPR:$rs3, uimm5:$shamt)>; -def : Pat<(i64 (riscv_fslw GPR:$rs3, GPR:$rs1, uimm5:$shamt)), +def : Pat<(riscv_fslw GPR:$rs3, GPR:$rs1, uimm5:$shamt), (FSRIW GPR:$rs1, GPR:$rs3, (ImmSubFrom32 uimm5:$shamt))>; } // Predicates = [HasStdExtZbt, IsRV64] let Predicates = [HasStdExtZbb, IsRV64] in { -def : Pat<(i64 (riscv_clzw GPR:$rs1)), (CLZW GPR:$rs1)>; -def : Pat<(i64 (riscv_ctzw GPR:$rs1)), (CTZW GPR:$rs1)>; +def : Pat<(riscv_clzw GPR:$rs1), (CLZW GPR:$rs1)>; +def : Pat<(riscv_ctzw GPR:$rs1), (CTZW GPR:$rs1)>; def : Pat<(i64 (ctpop (and GPR:$rs1, 0xFFFFFFFF))), (CPOPW GPR:$rs1)>; } // Predicates = [HasStdExtZbb, IsRV64]