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JDevlieghere accepted D100846: [lldb] Don't leak LineSequence in PDB parsers.

LGTM

Tue, Apr 20, 8:43 AM · Restricted Project
ab committed rGa0573b6c1003: [AArch64] Bump apple-latest CPU alias to apple-a14. (authored by ab).
[AArch64] Bump apple-latest CPU alias to apple-a14.
Tue, Apr 20, 8:42 AM
ab committed rGcedb5b06df1b: [AArch64] Don't always override CPU for arm64e. (authored by ab).
[AArch64] Don't always override CPU for arm64e.
Tue, Apr 20, 8:42 AM
ab committed rGa8a3a4379247: [AArch64] Add apple-m1 CPU, and default to it for macOS. (authored by ab).
[AArch64] Add apple-m1 CPU, and default to it for macOS.
Tue, Apr 20, 8:42 AM
aganea added a comment to D100755: [llvm-rc] [3/4] Run clang to preprocess input files.

Thanks for adding this Martin!

I'd really like to see a simple test running from the Clang side as well! Like calling llvm-rc with a file that requires preprocessing:

That sounds like a good idea, as there's indeed a gap in testing at that spot right now.

What would be the most appropriate place under clang/test for it?

Maybe under clang\test\Preprocessor ?

Tue, Apr 20, 8:40 AM · Restricted Project
Eric added a comment to D100299: Be lazier about loading .dwo files.

Let me know if I should request this review from someone else. It is important for scalability, as this change, in combination with my follow-up change (https://reviews.llvm.org/D100771) eliminate the need to load all .dwo files in the most common debugging scenarios.

Tue, Apr 20, 8:38 AM
thakis accepted D100744: Use SmallVector instead of std::vector to manage storage of llvm::BitVector.

Thanks!

Tue, Apr 20, 8:38 AM · Restricted Project
LLVM GN Syncbot <llvmgnsyncbot@gmail.com> committed rGd51b22d782ee: [gn build] Port 120fa8293e22 (authored by LLVM GN Syncbot <llvmgnsyncbot@gmail.com>).
[gn build] Port 120fa8293e22
Tue, Apr 20, 8:38 AM
thakis accepted D100804: [lld-macho] Support subtractor relocations that reference sections.
Tue, Apr 20, 8:37 AM · Restricted Project, Restricted Project
bader added inline comments to D89909: [SYCL] Implement SYCL address space attributes handling.
Tue, Apr 20, 8:37 AM · Restricted Project, Restricted Project
stellaraccident added a comment to D100859: [mlir] use absolute import path in python op bindings generator.

And here in npcomp: https://github.com/llvm/mlir-npcomp/blob/main/python/npcomp/dialects/_ods_common.py

Tue, Apr 20, 8:37 AM · Restricted Project
yaxunl added a comment to D100404: Add no_pop variant to pragma attributes.

there are still pre-merge failures. you may need update your test

Tue, Apr 20, 8:36 AM
thakis accepted D100848: [lld-macho] Ensure segments are laid out contiguously.
Tue, Apr 20, 8:36 AM · Restricted Project, Restricted Project
stellaraccident added a comment to D100859: [mlir] use absolute import path in python op bindings generator.

I'm other projects, we include an _ods_common.py trampoline in the project specific dialects directory: https://github.com/llvm/circt/blob/main/lib/Bindings/Python/circt/dialects/_ods_common.py

Tue, Apr 20, 8:35 AM · Restricted Project
thakis accepted D100755: [llvm-rc] [3/4] Run clang to preprocess input files.

This looks basically good to me.

Tue, Apr 20, 8:35 AM · Restricted Project
HsiangKai added inline comments to D100611: [RISCV] Add new attribute __clang_riscv_builtin_alias for intrinsics..
Tue, Apr 20, 8:34 AM · Restricted Project
arsenm accepted D100770: [AMDGPU] Allow multiple uses of the same literal.
Tue, Apr 20, 8:34 AM · Restricted Project
foad added inline comments to D100430: [AMDGPU][GlobalISel] Widen 1 and 2 byte scalar loads.
Tue, Apr 20, 8:33 AM · Restricted Project
zoecarver committed rG120fa8293e22: [libc++][nfc] Move iterator_traits and related into __iterator/iterator_traits. (authored by zoecarver).
[libc++][nfc] Move iterator_traits and related into __iterator/iterator_traits.
Tue, Apr 20, 8:32 AM
zoecarver closed D100686: [libc++][nfc] Move iterator_traits and related into __iterator/iterator_traits.h..
Tue, Apr 20, 8:32 AM · Restricted Project
stellaraccident added a comment to D100859: [mlir] use absolute import path in python op bindings generator.

Just a sec: we solved this on the circt side - need to look at how.

Tue, Apr 20, 8:32 AM · Restricted Project
arsenm committed rG14b03b4aadee: GlobalISel: Check for powers of 2 for inverse funnel shift lowering (authored by arsenm).
GlobalISel: Check for powers of 2 for inverse funnel shift lowering
Tue, Apr 20, 8:30 AM
HsiangKai added a comment to D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors..

We want this to support the segment load/store intrinsics defined here https://github.com/riscv/rvv-intrinsic-doc/blob/master/intrinsic_funcs/03_vector_load_store_segment_instructions_zvlsseg.md These return 2 to 8 vectors that have been loaded into consecutive registers. I believe SVE has similar instructions. I believe SVE represents these using types wider than their normal scalable vector types and relies on the type legalizer to split them up in the backend. This works for SVE because there is only one known minimum size for all scalable vector types so the type legalizer will always split down to that minimum type.

Thanks for providing the context!

For RISC-V vectors we already use 7 different sizes of scalable vectors to represent the ability of our instructions to operate on 2, 4, or 8 registers simultaneously. And for 1/2, 1/4, and 1/8 fractional registers. The segment load/store instructions add an extra dimension where they can produce/consume 2, 3, or 4 pairs of registers or 2 quadruples, for examples. Following the SVE strategy would give us ambiguous types for the type legalizer.

How does that look in terms of IR? Is the number of registers somehow represented in the (LLVM IR) vector type? Or are the types the same, but the compiler generates different code depending on what mode is set? For SVE we know we can split the vector because <vscale x 8 x i32> is twice the size of <vscale x 4 x i32>, regardless of the value for vscale. Indeed we know SVE vectors area multiple of 128bits, and therefore that <vscale x 4 x i32> is legal. In order to make any assumptions about splitting/legalization, the compiler will need to know which types are legal, and so would expect the compiler to know the mode (2, 4 ,8) for RVV when generating the code, and therefore have similar knowledge about which types are legal and how the vectors are represented/split into registers. How does that lead to ambiguous types?

To solve this we would like to use a struct for the segment load/stores to separate them in IR. Since clang needs an address for every variable and needs to be able to load/store them we need to support load/store/alloca.

These (C/C++-level) intrinsics are probably implemented using target-specific intrinsics or perhaps a common LLVM IR intrinsic like masked.load, which should be able to take/return a struct with scalable members after D94142. If so, it should be possible to handle this in Clang by emitting extractvalue instructions and storing each member individually. That would avoid any changes to LLVM IR. Is that something you've considered?

Tue, Apr 20, 8:30 AM · Restricted Project
ldionne committed rG9f01ac3b3257: [libcxx] makes `iterator_traits` C++20-aware (authored by zoecarver).
[libcxx] makes `iterator_traits` C++20-aware
Tue, Apr 20, 8:30 AM
ldionne closed D99855: [libcxx] makes `iterator_traits` C++20-aware.
Tue, Apr 20, 8:30 AM · Restricted Project
ABataev added a reverting change for rGdaf6e18c55c2: [SLP] Add detection of shuffled/perfect matching of tree entries.: rGb82344a01949: Revert "[SLP] Add detection of shuffled/perfect matching of tree entries.".
Tue, Apr 20, 8:30 AM
ABataev committed rGb82344a01949: Revert "[SLP] Add detection of shuffled/perfect matching of tree entries." (authored by ABataev).
Revert "[SLP] Add detection of shuffled/perfect matching of tree entries."
Tue, Apr 20, 8:30 AM
ABataev added a reverting change for D100495: [SLP] Add detection of shuffled/perfect matching of tree entries.: rGb82344a01949: Revert "[SLP] Add detection of shuffled/perfect matching of tree entries.".
Tue, Apr 20, 8:30 AM · Restricted Project
erik.pilkington added a comment to D90188: Add support for attribute 'using_if_exists'.

Does anyone have any remaining concerns or a desire to take another pass through this patch? If not, then I'll commit this later this week on Aaron's LGTM.

Tue, Apr 20, 8:29 AM
thakis accepted D100833: [llvm-cvtres] Reduce the set of dependencies of llvm-cvtres. NFC..

Nice!

Tue, Apr 20, 8:28 AM · Restricted Project
olestrohm requested review of D100860: [C++4OpenCL] Add missing OpenCL specific diagnostics in templates.
Tue, Apr 20, 8:28 AM · Restricted Project
fhahn added inline comments to D100257: [VPlan] Add VPUserID to distinguish between recipes and others..
Tue, Apr 20, 8:27 AM · Restricted Project
StephenTozer updated the diff for D100572: [DebugInfo] Ensure DIArgList in bitcode has no null or forward metadata refs.

In the previous version of the patch, the actual Constant values used by the ConstantAsMetadata arguments to DIArgList were not being enumerated until the function that used them was incorporated, which resulted in incorrect bitcode output (all constant values in the bitcode are expected to appear at the module level).

Tue, Apr 20, 8:26 AM · Restricted Project, debug-info
Eric updated the diff for D100771: support on-demand indexing in ManualDWARFIndex.

Rebased to not depend on other cl

Tue, Apr 20, 8:25 AM
dmgreen committed rG21a8b9d9e9e1: [ARM] Limit PerformExtractEltToVMOVRRD to when f64 is legal. (authored by dmgreen).
[ARM] Limit PerformExtractEltToVMOVRRD to when f64 is legal.
Tue, Apr 20, 8:25 AM
craig.topper added a comment to D99083: [RISCV] Introduce floating point control and state registers.

I don't think we should have unused pseudo instructions since they should all have lit tests. So if they can't be tested soon, they should be added when they are needed.

Patches that implement FLT_ROUNDS_ (D90854) and SET_ROUNDING (D91242) use these instructions and they have tests. It it enough?

Tue, Apr 20, 8:25 AM · Restricted Project
jhuber6 updated the diff for D99202: [OpenMP] Add OpenMPOpt as a Module pass.

Fixing tests.

Tue, Apr 20, 8:24 AM · Restricted Project
fhahn updated the diff for D100257: [VPlan] Add VPUserID to distinguish between recipes and others..

Add comment about the Other ID type, making clear that currently there are VPUsers in VPBlockBase, but in the future Other should only be used for live-outs.

Tue, Apr 20, 8:24 AM · Restricted Project
ldrumm added a comment to D99334: [TransformUtils] Don't generate invalid llvm.dbg.cu .

Why would code handling llvm.dbg.cu need to add an if statement? I'd expect it to walk through whatever's in llvm.dbg.cu and if there's nothing it'd be fine with that?

Tue, Apr 20, 8:19 AM · Restricted Project
keith updated the diff for D100681: llvm-objdump: add --rpaths to macho support.

Update test formatting

Tue, Apr 20, 8:18 AM · Restricted Project